ASIC Verification Engineer (Block and IP level verification)
Creation of verification environments, pre-silicon functional verification at the block, chip and system level, reference modeling and post-silicon validation.
Develop environment and test cases to verify hardware security designs (previous security experience not required but a plus).
" 6+ years of experience in design verification with a proven track record of full verification cycle on complex SoC IPs and/or systems.
" System Verilog and UVM
" In depth knowledge of verification principles, testbenches, stimulus generation, UVM, and coverage
" Substantial background in creating simulation environments, developing tests, and debugging designs
" Solid understanding of chip and/or computer architecture
" Scripting language such as Python, Ruby, or Perl
" The ideal candidate is also passionate in developing systematic and efficient methods to detecting hardware/software vulnerabilities.
" Hardware security IP and SOC level verification
" Experience with secure hardware design for embedded systems
" Firmware development experience, with secure and non-secure boot flow
" Experience with hardware emulation or FPGAs